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Gone are the days when process shrinking was considered as the primary driver of product innovation and improved system performance. The path most are taking leads to the world of “More than Moore.” Vertical Stacking of heterogeneous chips and chiplets is the name of the game. It will have a significant impact on applications that require ultra-high-performance and low power, such as multi-core CPUs, GPUs, packet buffers/routers, smartphones, AI/ML applications, etc. It helps to cram more functionality into much smaller form factors while improving performance and reducing costs. Cadence has created a four-part webinar series, explaining how to properly plan 2.5-D/3-D systems, while meeting system-level power and thermal analysis requirements through an integrated 3D-IC solution.
With existing tools and methodologies, it is possible to do a “die-by-die” design and connect pieces on an interposer or RDL layer. This approach is used for today’s multi-chiplet designs where different chiplets and packages are aggregated at the top level, which involves a lot of file passing and database format exchanges. However, there is additional verification at the system level after such integrations.
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A successful design environment for such multi-chiplet systems should be integrated, yet modular. It should have the ability to assemble multiple chiplets for a bottom-up approach while looking at the system. In other words, it should capture design intent upfront, support abstraction for system planning along with early feedback from system-level effects like thermal and power dissipation and achieve system convergence through seamless implementation and analysis while taking into account chip and packaging effects.
3D-IC technology and advanced packaging technologies allow designers to integrate multiple homogenous and heterogeneous die/chiplets, such as logic, memory, analog, and RF, into a single design.
Challenges in 3D IC design
Although several point tools are available today to design a 3D-IC, it’s up to each design team to develop their methodologies to integrate the flow. This makes designing a 3D-IC today quite a challenge. Design teams are forced to spend more time writing scripts and customizing the design flow for each design and less time doing design work. The four big challenges that arise when pivoting from a single SoC to a multi-chip(let) architecture are as follows:
- Top-level/system-level heterogeneous design aggregation, planning, and optimization
- Co-design and co-analysis of the die, chiplets, packaging, and PCB
- Early pre-layout thermal analysis
- A common platform that seamlessly integrates these technologies
New 3D implementation and system planning challenges emerge as chip stacking creates new complexities related to different components of the stack and the system, with extra considerations to be given to mechanical, electrical, and thermal aspects of the whole stacked system. Designers need a solution that can aggregate all the required functionality into a single design platform.
A successful 3D-IC design environment will capture the top-level design intent upfront, support abstraction with the early estimation of power/thermal, and achieve convergence through implementation, extraction, timing closure, test, analysis, and packaging.
Cadence Integrity 3D-IC
The Cadence Integrity 3D-IC platform is the industry’s first integrated solution for system planning, implementation, and signoff of heterogeneous and homogenous 2.5D and 3D stacked designs that allow the integration of multiple chiplets. It leverages Cadence’s industry-leading implementation and signoff technologies for digital, analog, and packaging through a unified hierarchical database. With system analysis and smart physical verification feedback provided early in the planning and implementation flow, the Integrity 3D-IC platform delivers true system-driven PPA while avoiding costly overdesign and margining of individual chiplets in a 3D-IC system.
- Single-cockpit, high-capacity 3D design, planning and implementation platform for handling all types of 3D-IC stacks enabled by foundries
- Powerful cross-platform co-design capabilities with the Cadence Virtuoso and Allegro environments
- Elegant flow manager to set up early power-thermal analysis, cross-die static timing analysis, and inter-die physical verification
- Unique hierarchical planning and optimization capabilities for system-level design through the system planner
- Complete stack management, chip-to-package signal mapping, and advanced bump and TSV planning through real-time TCL-based direct integration with Cadence’s Innovus Implementation System
- Powerful 2D to 3D exploration flows for homogenous stacked die exploration with memory-on-logic and logic-on-logic exploration
- Efficient on-disk database for hierarchical multi-level representation of each tier
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To learn more register and join for webinar series as mentioned below, there will be knowledge-rich sessions about planning, implementation, and analysis platform to take the full system view and perform system-driven optimization of performance, power, and area (PPA) for chiplets.
- CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
- CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
- CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
- CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
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